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參數(shù)資料
| 型號： | TLV320AIC10CGQE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | MICRO, PLASTIC, BGA-80 |
| 文件頁數(shù)： | 5/57頁 |
| 文件大小： | 454K |
| 代理商： | TLV320AIC10CGQE |
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1–7
1.5
Terminal Functions (Continued)
TERMINALS
I/O
NAME
NO.
I/O
DESCRIPTION
NAME
PFB
GQE
I/O
DESCRIPTION
MCLK
20
J5
I
Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.
M/S
27
F8
I
Master/slave select input. When M/S is high, the device is the master, and when is low, it is a slave.
NC
18, 28,
31, 32,
35, 36,
37, 39,
41, 44
A6, A7,
C9, C8,
F9
No connection
OUTM
9
F2
O
DACs inverting output. OUTM is functionally identical with and complementary to OUTP.
OUTP
8
F1
O
DACs noninverting output. OUTP can also be used alone for single-ended operation.
PWRDWN
12
H1
I
Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial
interface is disabled, and most of the high-speed clocks are disabled. However, all register values are
sustained and the device resumes full-power operation without reinitialization when PWRDWN is
pulled high again. PWRDWN resets the counters only and preserves the programmed register
contents. See paragraph 2.2.2 for more information.
RESET
13
J2
I
The reset function is provided to initialize all the internal registers to their default values. The serial
port can be configured to the default state accordingly. See Appendix A, Register Set, and Subsection
2.2, Reset and Power-Down Functions for detailed descriptions. All RESET pins of devices in
cascade must be tied together.
SCLK
19
H5
I/O
Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval.
When configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync
signal frequency by 256 (cascade devices < 5) or 512 (cascade devices > 4). When configured as an
input (M/S low), SCLK is generated externally and must be synchronous with the master clock and
frame sync.
VMID
43
A4
O
Reference voltage output at AVDD/2
1.6
Definitions and Terminology
Data transfer interval
The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks
and the data transfer is initiated by the falling edge of the FS signal.
Signal data
This refers to the input signal and all of the converted representations through the ADC
channel, and the signal through the DAC channel to the analog output. This is in contrast
with the purely-digital software control data.
Primary
communication
Primary communication refers to the digital data-transfer interval. Since the device is
synchronous, the signal data words from the ADC channel and to the DAC channel occur
simultaneously.
Secondary
communication
Secondary communication refers to the digital control and configuration data-transfer
interval into DIN, and the register read-data cycle from DOUT. The data transfer occurs
when requested by hardware or software.
SPI
Serial peripheral interface standard set by Motorola
Frame/pulse sync
Frame/pulse sync refers only to the falling edge of the signal FS that initiates the
data-transfer interval. The primary FS starts the primary communication, and the
secondary FS starts the secondary communication.
Frame/pulse sync and
sampling period
Frame/pulse sync and sampling period is the time between falling edges of successive
primary FS signals and it is always equal to 256xSCLK if the number of cascading devices
is less than 5, or 512 xSCLK if the number of cascading devices is greater than 4.
fs
The sampling frequency
ADC channel
ADC channel refers to all signal-processing circuits between the analog input and the
digital conversion result at DOUT.
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