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參數資料
| 型號： | TLV320AIC14I |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | PLASTIC, TSSOP-30 |
| 文件頁數： | 26/54頁 |
| 文件大小： | 450K |
| 代理商： | TLV320AIC14I |
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4–3
4.4
Control Register 4
D7
D6
D5
D4
D3
D2
D1
D0
FSDIV
MNP
R/W
NOTE: R = Read, W = Write
Table 4–4. Control Register 4 Bit Summary
BIT
NAME
RESET
VALUE
FUNCTION
D7
FSDIV
0
Frame sync division factor
FSDIV = 0 To write value of P to bits D2-D0 and value of N to bits D6-D3
FSDIV = 1 To write value of M to bits D6-D0
D6–D0
MNP
—
Divider values of M,N, and P to be used in junction with the FSDIV bit for calculation of FS frequency according
to the formula FS = MCLK / (16xMxNxP)
M = 1,2,
…,128 Determined by D6-D0 with FSDIV = 1
D7-D0 = 10000000 M = 128
D7-D0 = 10000001 M = 1
D7-D0 = 11111111
M = 127
N = 1,2,
…,16 Determined by D6-D3 with FSDIV = 0
D7-D0 = 00000xxx N = 16
D7-D0 = 00001xxx N = 1
D7-D0 = 01111xxx
N = 15
P = 1,2,
…,8
Determined by D2-D0 with FSDIV = 0
D7-D0 = 0xxxx000 P = 8
D7-D0 = 0xxxx001 P = 1
D7-D0 = 0xxxx111
P = 7
NOTES:
1. It takes 2 sampling periods to update new values of M,N, and P.
2. In register read operation, first read receives N and P values and second read receives M value.
3. M(default) = 16, N(default) = 6, P(default) = 8
4. If P = 8, the device enters the coarse sampling mode as described in Section 3.1 Operating Frequencies
4.5
Control Register 5A
D7
D6
D5
D4
D3
D2
D1
D0
0
ADGAIN
R/W
NOTE: R = Read, W = Write
Table 4–5. Control Register 5A Bit Summary
BIT
NAME
RESET
VALUE
FUNCTION
D7-D6
Control
Register 5A
00
ADC programmable gain amplifier
D5-D0
ADGAIN
101010
A/D converter gain (see Table 4–6)
NOTES:
5. In register read operation, first read receives ADC gain value, second read receives DAC gain value, third read receives register
5C contents, and fourth read receives register 5D contents.
6. PGA default value = 101010b (0dB) for both ADC and DAC.
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