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參數資料
| 型號： | TLV320AIC23BRHD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC28 |
| 封裝： | GREEN, PLASTIC, QFN-28 |
| 文件頁數： | 17/54頁 |
| 文件大小： | 795K |
| 代理商： | TLV320AIC23BRHD |
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35
Sample Rate Control (Address: 0001000)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
CLKOUT
CLKIN
SR3
SR2
SR1
SR0
BOSR
USB/Normal
Default
0
1
0
CLKIN
Clock input divider
0 = MCLK
1 = MCLK/2
CLKOUT
Clock output divider
0 = MCLK
1 = MCLK/2
SR[3:0]
Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
BOSR
Base oversampling rate
USB mode:
0 = 250 fs
1 = 272 fs
Normal mode:
0 = 256 fs
1 = 384 fs
USB/Normal
Clock mode select:
0 = Normal
1 = USB
X
Reserved
Digital Interface Activation (Address: 0001001)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
RES
X
ACT
Default
0
ACT
Activate interface
0 = Inactive
1 = Active
X
Reserved
Reset Register (Address: 0001111)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
RES
Default
0
RES
Write 000000000 to this register triggers reset
3.2
Analog Interface
3.2.1
Line Inputs
The TLV320AIC23B has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs
have independently programmable volume controls and mutes. Active and passive filters for the two channels
prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range
is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage AVDD. To avoid distortions,
it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of software write
cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown
in Figure 3-3.
R
2
R1
C1
C2
+
CDIN
LINEIN
AGND
Where:
R1 = 5 k
R2 = 5 k
C1 = 47 pF
C2 = 470 nF
Figure 33. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the AIC23B
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
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| TLV320AIC23BRHDG4 | 功能描述:接口—CODEC L-P Stereo CODEC with HP Amplifier RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC23BRHDR | 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC23BRHDRG4 | 功能描述:接口—CODEC Lo-Pwr Highly Integrated Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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