- 您現在的位置：買賣IC網 > PDF目錄98253 > TLV320AIC28IRGZRG4 (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQCC48 PDF資料下載
參數資料
| 型號： | TLV320AIC28IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, QFN-48 |
| 文件頁數： | 11/85頁 |
| 文件大小： | 1053K |
| 代理商： | TLV320AIC28IRGZRG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
19
D Word Select Signals
The word select signal (WCLK) indicates the channel being transmitted:
— WCLK = 0: left channel for I2S mode;
— WCLK = 1: right channel for I2S mode.
For other modes refer to the timing diagrams below.
D Bitclock (BCLK) Signal
In addition to being programmable as master or slave mode, the BCLK can also be configured in two transfer
modes, 256-S transfer mode and continuous transfer mode, which are described below. These modes are
set using bit D12 of control register 06H/page 2.
D 256-S Transfer Mode
In the 256-S mode, the BCLK rate always equals 256 times the WCLK frequency. In the 256-S mode, the
combination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5D0 of control register 00H/page
2) and left-justified mode is not supported. If IOVDD is equal to 1.1 V, then ADC/DAC sampling rate should be
less than 39 kHz for all modes except the left justified mode where it should be less than 24 kHz.
D Continuous Transfer Mode
In the continuous transfer mode, the BCLK rate always equals two-word length times the frequency of
WCLK.
D Right Justified Mode
In right-justified mode, the LSB of left channel is valid on the rising edge of BCLK preceding, the falling edge
on WCLK. Similarly the LSB of right channel is valid on the rising edge of BCLK preceding the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n
n1
1
0
n
n1
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n2
2
n2
Figure 15. Timing Diagram for Right-Justified Mode
相關PDF資料 |
PDF描述 |
|---|---|
| TLV320AIC28RGZR | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| TLV320AIC28RGZ | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| TLV320AIC28IRGZG4 | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| TLV320AIC29IRGZRG4 | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| TLV320AIC29IRGZR | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV320AIC28RGZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLV320AIC28RGZR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLV320AIC29 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLV320AIC29_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STWREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLV320AIC29_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO AUDIO CODEC WITH INTEGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
發布緊急采購，3分鐘左右您將得到回復。