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參數(shù)資料
| 型號： | TLV320AIC3107YZFR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2 CHANNEL, AUDIO AMPLIFIER, PBGA42 |
| 封裝： | 3.50 X 3 MM, 0.50 MM PITCH, WSCP-42 |
| 文件頁數(shù)： | 21/94頁 |
| 文件大小： | 1183K |
| 代理商： | TLV320AIC3107YZFR |
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H(z) +
N0 ) N1
z*1
32768 * D1
z*1
(1)
DIGITAL AUDIO PROCESSING FOR RECORD PATH
AudioSerialBusInterface
PGA
0/+59.5dB
0.5dBsteps
ADC
+
DAC
L
Volume
Control
DIN
DOUT
BCLK
WCLK
DINL
DINR
DOUTL
DOUTR
ADC
PGA
0/+59.5dB
0.5dBsteps
+
DACR
Volume
Control
Effects
AGC
RecordPath
DAC
Powered
Down
DAC
Powered
Down
Effects
SW-D1
SW-D2
SW-D3
SW-D4
LeftChannel
AnalogInputs
RightChannel
AnalogInputs
AUTOMATIC GAIN CONTROL (AGC)
SLOS545B – NOVEMBER 2008 – REVISED JANUARY 2009........................................................................................................................................... www.ti.com
Programming the Left channel is done by writing to Page 1, Registers 65-70, and the right channel is
programmed by writing to Page 1, Registers 71-76. After the coefficients have been loaded, these ADC high
pass filter coefficients can be selected by writing to Page 0, Register 107, D7-D6, and the high pass filter can be
enabled by writing to Page 0, Register 12, bits D7-D4.
In applications where record only is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or
notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the
ADC output data through the digital signal processing blocks. Since the DAC's Digital Signal Processing blocks
are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital
processing and are located on Page 1, Registers 1-52. This record only mode is enabled by powering down both
DACs by writing to Page 0, Register 37, bits D7-D6 (D7=D6=”0”). Next, enable the digital filter pathway for the
ADC by writing a “1” to Page 0, Register 107, bit D3. (Note, this pathway is only enabled if both DACs are
powered down.) This record only path can be seen in Figure 24.
Figure 24. Record Only Mode With Digital Processing Path Enabled
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes loud or weak, such as when a person speaking
28
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3107
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| TLV320AIC3110 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Audio Codec With Audio Procsessing and Stereo Class-D Speaker Amplifier |
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| TLV320AIC3110IRHBT | 功能描述:接口—CODEC Low-Pwr Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3111 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Audio Codec With Embedded miniDSP and Stereo Class-D Speaker Amplifier |
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