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參數資料
| 型號： | TLV320AIC3253IRGET |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封裝： | 4 X 4 MM, PLASTIC, QFN-24 |
| 文件頁數： | 32/35頁 |
| 文件大小： | 738K |
| 代理商： | TLV320AIC3253IRGET |
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SLOS631 – MARCH 2010
www.ti.com
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
AVdd to AVss
–0.3 to 2.2
V
DVdd to DVss
–0.3 to 2.2
V
IOVDD to IOVSS
–0.3 to 3.9
V
LDOIN to AVss
–0.3 to 3.9
V
Digital Input voltage
–0.3 to IOVDD + 0.3
V
Analog input voltage
–0.3 to AVdd + 0.3
V
Operating temperature range
–40 to 85
°C
Storage temperature range
–55 to 125
°C
Junction temperature (TJ Max)
105
°C
S-XBGA NanoFree
Power dissipation
(TJ Max – TA)/ qJA
W
package (YZK)
qJA Thermal impedance
48
C/W
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM
MAX
UNIT
LDOIN(1)
Power Supply Voltage Range
Referenced to AVss(2)
1.9
3.6
V
AVdd
1.5
1.8
1.95
IOVDD
Referenced to IOVSS(2)
1.1
3.6
DVdd
Referenced to DVss(2)
1.65
1.8
1.95
DVdd(3)
1.26
1.8
1.95
PLL Input Frequency
Clock divider uses fractional divide
10
20
MHz
(D > 0), P=1, DVdd ≥ 1.65V (See table in SLAU303,
Maximum TLV320AIC3253 Clock Frequencies)
Clock divider uses integer divide
0.512
20
MHz
(D = 0), P=1, DVdd ≥ 1.65V (Refer to table in
SLAU303, Maximum TLV320AIC3253 Clock
Frequencies)
MCLK
Master Clock Frequency
MCLK; Master Clock Frequency; DVdd ≥ 1.65V
50
MHz
SCL
SCL Clock Frequency
400
kHz
HPL,
Stereo headphone output load
Single-ended configuration
14.4
16
HPR
resistance
Headphone output load resistance
Differential configuration
24.4
32
CLout
Digital output load capacitance
10
pF
Cref
Reference decoupling capacitor (4)
1
10
F
(1)
Minimum spec applies if LDO is used. Minimum is 1.5V if LDO is not enabled. Using the LDO below 1.9V degrades LDO performance.
(2)
All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground
signals.
(3)
At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAU303, Maximum TLV320AIC3253 Clock
Frequencies for details on maximum clock frequencies.
(4)
For Cref< 10F, performance may decrease. Electrical characteristics are based on Cref=10F.
6
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3253
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