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參數(shù)資料
型號: TLV320AIC32IRHBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 22/72頁
文件大小: 4594K
代理商: TLV320AIC32IRHBG4
www.ti.com
LB1
RB2
Atten
LB2
L
R
TOLEFTCHANNEL
TO RIGHT CHANNEL
DIGITAL INTERPOLATION FILTER
DELTA-SIGMA AUDIO DAC
TLV320AIC32
SLAS479A – AUGUST 2005 – REVISED SEPTEMBER 2005
Figure 27. Architecture of the Digital Audio Processing When 3-D Effects are Enabled
It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
While new coefficients are being written to the device over the control port, it is possible that a filter using
partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable
audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of
effects can be entirely avoided.
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/Fs. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the
programmable interpolation capability, the Fsref should be programmed to a higher rate (restricted to be in the
range of 39 kHz to 53 kHz when the PLL is in use), and the actual Fs is set using the NDAC divider. For
example, if Fs = 8 kHz is required, then Fsref can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures
that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
The stereo audio DAC incorporates a third order multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a
continuous time RC filter. The analog FIR operates at a rate of 128
× Fsref (6.144 MHz when Fsref = 48 kHz,
5.6448 MHz when Fsref = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.
29
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TLV320AIC32IRHBR 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC32IRHBRG4 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC32IRHBT 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC32IRHBTG4 功能描述:接口—CODEC Lo-Pwr Stereo Codec w/6 Inp 6 Otp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC33 制造商:BB 制造商全稱:BB 功能描述:LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
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