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參數資料
| 型號： | TLV320DAC3202IYZJR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | VOLUME CONTROL CIRCUIT, PBGA20 |
| 封裝： | 2 X 2.50 MM, 0.50 MM PITCH, WCSP-20 |
| 文件頁數： | 7/20頁 |
| 文件大小： | 435K |
| 代理商： | TLV320DAC3202IYZJR |
www.ti.com
SLAS726A – SEPTEMBER 2010 – REVISED JANUARY 2011
PCB DEVELOPMENT
The following table explains the PCB recommendations. In addition, it is recommended to split the ground plane
into analog and digital segment for clean and noisy signals. They should be connected only in a single point to
avoid ground loop.
Table 11. PCB Recommendations
BALL NAME
DESCRIPTION
LAYOUT RECOMMENDATIONS
AVSS
Analog ground
VANAG
Connected to VANA via capacitor
Connect to output capacitor with < 10 m
Ω.
VANA
Analog LDO output
Connect to output capacitor with < 10 m
Ω.
Minimize the resistance path with adequate decoupling very
DVDD
IO/Digital supply
close to the ball.
CFLYP
FLY capacitor "+" terminal
Connect to positive side of output capacitor with < 10 m
Ω.
Connect to AVSS via output capacitor. The capacitor trace on
the AVSS side of the capacitor should not be connected to
VREF
Analog reference output
GND plane directly but at the AVSS pin. See application
diagram.
Minimize the resistance path with adequate decoupling very
AVDD
2.3-V to 4.8-V battery input
close to the ball.
Minimize the resistance path with adequate decoupling very
VPOW
CP LDO output
close to the ball.
Connect to separate GND plane for noisy signals, i.e. PLL
DVSS
Digital ground
and interfaces. Connect the two planes in a single point to
avoid GND loop.
CFLYN
FLY capacitor "-" terminal
Connect to negative side of output capacitor with < 10 m
Ω.
Keep this away from clean quite signal paths over the digital
SDA
I2C data
GND plane.
Keep this away from clean quite signal paths over the digital
SCL
I2C CLK in
GND plane.
Trace impedance must be very small, < 60 m
Ω. This is
HSOUTG
HS feedback ground
important for cross talk reduction. Connection to GND plane
must be at IC ball.
Decouple this path to DVSS with trace impedance of
HSVDD
HS positive supply
< 20 m
Ω.
Must be routed in differential pair with GNDHS to the
HSOUTL
HS output left
connector. Match the impedances and as small as possible.
DIN
I2S downlink data
Keep this trace away from quite GND/signal traces.
WCLK
I2S word clock
Keep this trace away from quite GND/signal traces.
BCLK
I2S bit clock
Keep this trace away from quite GND/signal traces.
Must be routed in differential pair with GNDHS to the
HROUTR
HS output right
connector. Match the impedances and as small as possible.
Decouple this path to DVSS with trace impedance of
HSVSS
HS negative supply
< 20 m
Ω.
Copyright 2010–2011, Texas Instruments Incorporated
15
Product Folder Link(s): TLV320DAC3202
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| TLV320DAC3203IRGET | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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