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參數資料
型號: TLV5510IPWLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24
封裝: PLASTIC, TSSOP-24
文件頁數: 6/19頁
文件大小: 307K
代理商: TLV5510IPWLE
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
functional description (continued)
The MSB comparator block converts on the falling edge of each applied clock cycle. The LSB comparator blocks
CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The
timing diagram of the conversion algorithm is shown in Figure 19.
analog input operation
The analog input stage to the TLV5510 is a chopper-stabilized comparator and is equivalently shown below:
VDDA
ANALOG IN
S1
Vref(N)
φ1
φ2
S3
φ1
Cs
To Encoder Logic
φ2
S2
φ1
Cs
To Encoder Logic
φ2
S(N)
φ1
Cs
To Encoder Logic
Figure 20. External Connections for Using the Internal Reference Resistor Divider
Figure 20 depicts the analog input for the TLV5510. The switches shown are controlled by two internal clocks,
φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,
φ1, S1 is closed and the input signal is applied to one side of the sampling capacitor, Cs. Also during the sampling
period, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage
is developed across Cs. During the comparison phase, φ2, S1 is switched to the appropriate reference voltage
for the bit value N, i.e., Vref(N). S2 is opened and Vref(N) – VCs toggles the comparator output to the appropriate
digital 1 or 0. The small resistance values for the switch, S1, and small value of the sampling capacitor combine
to produce the wide analog input bandwidth of the TLV5510. The source impedance driving the analog input
of the TLV5510 should be less than 100
across the range of input frequency spectrum.
reference inputs – REFB, REFT, REFBS, REFTS
The range of analog inputs that can be converted are determined by REFB and REFT, REFT being the
maximum reference voltage and REFB being the minimum reference voltage. The TLV5510 is tested with
REFT = 2.5 V or 2 V and REFB = 0.5 V or 0 V producing a 2-V full-scale range. The TLV5510 can operate with
REFT – REFB = 2.4 V, but the power dissipation in the reference resistor increases significantly (49 mW at 3.3 V
nominally). It is recommended that a 0.1
F capacitor be attached to REFB and REFT whether using externally
or internally generated voltages.
相關PDF資料
PDF描述
TLV5535IPWLE 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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TLV5535IPWR 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV5535IPWRG4 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
相關代理商/技術參數
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