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參數資料
型號: TLV5510IPWR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24
封裝: PLASTIC, TSSOP-24
文件頁數: 7/20頁
文件大小: 330K
代理商: TLV5510IPWR
TLV5510
2.7-V TO 3.6-V 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS124C– DECEMBER 1997 – REVISED DECEMBER 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
internal reference voltage conversion
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals VDDA, REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible
without the use of external resistors.
The internal resistors are provided to develop REFT and REFB as listed in Table 1 (bias option 1) with only two
external connections. This is developed with a 3-resistor network connected to VDDA. When using this feature,
connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated with
VDDA is acceptable, this internal voltage reference saves space and cost (see Figure 21).
A second internal bias option (bias two option) is shown in Figure 22. Using this scheme REFB = AGND and
REFT is as shown in Table 1 (bias option 2). These bias voltage options can be used to provide the values listed
in the following table.
Table 1. Bias Voltage Options for Different VDDA
BIAS OPTION
VDDA
BIAS VOLTAGE
BIAS OPTION
VDDA
VREFB
VREFT
VREFT – VREFB
2.7 V
0.54
2.34
1.8
1
3 V
0.6
2.60
2
1
3.3 V
0.66
2.86
2.2
3.6 V
0.72
3.12
2.4
2.7 V
AGND
2.25
2
3 V
AGND
2.5
2
3.3 V
AGND
2.75
3.6 V
AGND
3
To use the internally-generated reference voltage, terminal connections should be made as shown in
Figure 21 or Figure 22.
R1
40
NOM
Rref
200
NOM
R2
60
NOM
VDDA
REFTS
REFT
REFB
REFBS
AGND
TLV5510
16
17
22
21
23
18
0.1
F
0.1
F
2.63 V dc
Figure 21. External Connections Using the Internal Bias One Option
相關PDF資料
PDF描述
TLV5510IPWLE 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24
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TLV5535IPWR 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
相關代理商/技術參數
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