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參數資料
| 型號： | TLV5580CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數： | 9/36頁 |
| 文件大小： | 478K |
| 代理商： | TLV5580CDW |
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TLV5580
8BIT, 80 MSPS LOW POWER A/D CONVERTER
SLAS205B DECEMBER 1998 REVISED OCTOBER 2003
www.ti.com
17
PRINCIPLE OF OPERATION
DIGITAL OUTPUTS
The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as
possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading
causes higher dynamic output currents and can increase noise coupling into the device’s analog front end. To
drive higher loads, use an output buffer is recommended.
When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC
delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the
specification section for more details.
LAYOUT, DECOUPLING AND GROUNDING RULES
It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated
performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.
TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier.
Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.
Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised.
As for power supplies, separate analog and digital supply terminals are provided on the device (AVDD/DVDD).
The supply to the digital output drivers is kept separate also (DRVDD). Lowering the voltage on this supply from
the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output
buffers.
Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply
and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the
TLV5580 EVM is recommended.
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| TLV5580CDWR | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| TLV5580CPWR | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| TLV5580IPWG4 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV5580CDWG4 | 功能描述:模數轉換器 - ADC 8Bit 80MSPS 1-Ch High Ch Band Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CDWR | 功能描述:模數轉換器 - ADC 8Bit 80MSPS 1-Ch High Ch Band Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CDWRG4 | 功能描述:模數轉換器 - ADC 8Bit 80MSPS 1-Ch High Ch Band Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CPW | 功能描述:模數轉換器 - ADC _ RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV5580CPWG4 | 功能描述:模數轉換器 - ADC 8B 80MSPS ADC Sgl Ch Hi Ch BW Lo Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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