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參數(shù)資料
型號(hào)： TLV5604CDR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝： GREEN, PLASTIC, SOIC-16
文件頁(yè)數(shù)： 28/31頁(yè)
文件大小： 572K
代理商： TLV5604CDR
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Output slew rate
CL = 100 pF, RL = 10 k,
VO 10% to 90%
Fast
5
V/
s
SR
Output slew rate
VO = 10% to 90%,
Vref = 2.048 V, 1024 V
Slow
1
V/
s
t
Output settling time
To
± 0.5 LSB, CL = 100 pF,
Fast
2.5
4
s
ts
Output settling time
,
L
,
RL = 10 k, See Notes 12 and 14
Slow
8.5
18
s
t ()
Output settling time code to code
To
± 0.5 LSB, CL = 100 pF,
Fast
1
s
ts(c)
Output settling time, code to code
,
L
,
RL = 10 k, See Note 13
Slow
2
s
Glitch energy
Code transition from 7FF to 800
10
nV-sec
SNR
Signal-to-noise ratio
Sinewave generated by DAC,
R f
l
1 024
3 V
d 2 048
5 V
68
S/(N+D)
Signal to noise + distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS,
65
dB
THD
Total harmonic Distortion
fs = 400 KSPS,
fOUT = 1.1 kHz sinewave,
CL = 100 pFRL =10k
–68
dB
SFDR
Spurious free dynamic range
CL = 100 pF,
RL = 10 k,
BW = 20 kHz
70
NOTES: 12. Settling time is the time for the output signal to remain within
± 0.5LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within
± 0.5LSB of the final measured value for a digital input code change
of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.
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