- 您現在的位置：買賣IC網 > PDF目錄98256 > TLV5604CPWG4 (TEXAS INSTRUMENTS INC) SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 PDF資料下載
參數資料
| 型號： | TLV5604CPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| 封裝： | GREEN, PLASTIC, TSSOP-16 |
| 文件頁數： | 29/31頁 |
| 文件大小： | 572K |
| 代理商： | TLV5604CPWG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–FS)
Setup time, CS low before FS
↓
10
ns
tsu(FS–CK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16–FS)
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
10
ns
tsu(C16–CS)
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
10
ns
twH
Pulse duration, SCLK high
25
ns
twL
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
Pulse duration, FS high
20
ns
PARAMETER MEASUREMENT INFORMATION
12
3
4
5
15
16
D15
D14
D13
D12
D1
D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
tsu(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| TLV5604ID | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| TLV5604CPWR | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| TLV5604CPWLE | QUAD, SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| TLV5604IPWLE | QUAD, SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| TLV5604IDRG4 | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV5604CPWR | 功能描述:數模轉換器- DAC 10-Bit 3 us Quad DAC Serial Input RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5604CPWRG4 | 功能描述:數模轉換器- DAC 10-Bit 3 us Quad DAC Serial Input RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5604D | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| TLV5604ID | 功能描述:數模轉換器- DAC 10bit Quad Serial RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5604ID | 制造商:Texas Instruments 功能描述:Digital-Analog Converter IC Interface Ty |
發布緊急采購，3分鐘左右您將得到回復。