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參數(shù)資料
型號(hào)： TLV5604CPWRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝： GREEN, PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 28/31頁(yè)
文件大小： 572K
代理商： TLV5604CPWRG4
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR
Output slew rate
CL = 100 pF, RL = 10 k,
VO 10% to 90%
Fast
5
V/
s
SR
Output slew rate
VO = 10% to 90%,
Vref = 2.048 V, 1024 V
Slow
1
V/
s
t
Output settling time
To
± 0.5 LSB, CL = 100 pF,
Fast
2.5
4
s
ts
Output settling time
,
L
,
RL = 10 k, See Notes 12 and 14
Slow
8.5
18
s
t ()
Output settling time code to code
To
± 0.5 LSB, CL = 100 pF,
Fast
1
s
ts(c)
Output settling time, code to code
,
L
,
RL = 10 k, See Note 13
Slow
2
s
Glitch energy
Code transition from 7FF to 800
10
nV-sec
SNR
Signal-to-noise ratio
Sinewave generated by DAC,
R f
l
1 024
3 V
d 2 048
5 V
68
S/(N+D)
Signal to noise + distortion
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
fs = 400 KSPS,
65
dB
THD
Total harmonic Distortion
fs = 400 KSPS,
fOUT = 1.1 kHz sinewave,
CL = 100 pFRL =10k
–68
dB
SFDR
Spurious free dynamic range
CL = 100 pF,
RL = 10 k,
BW = 20 kHz
70
NOTES: 12. Settling time is the time for the output signal to remain within
± 0.5LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within
± 0.5LSB of the final measured value for a digital input code change
of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.
相關(guān)PDF資料
PDF描述
TLV5604IDR SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604IPWR SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604CPWG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604ID SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV5604D 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5604ID 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10bit Quad Serial RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
TLV5604ID 制造商:Texas Instruments 功能描述:Digital-Analog Converter IC Interface Ty
TLV5604ID 制造商:Texas Instruments 功能描述:IC 10BIT DAC QUAD SMD SOIC16
TLV5604IDG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10bit Quad Serial RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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