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參數資料
| 型號： | TLV5604IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| 封裝： | GREEN, PLASTIC, TSSOP-16 |
| 文件頁數： | 9/31頁 |
| 文件大?。?/td> | 572K |
| 代理商： | TLV5604IPWR |
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;
set up the timer
;
timer period set by values in PRD and TDDR
;
period = (CLKOUT1 period)
× (1+PRD) × (1+TDDR)
;
examples for TMS320C203 with 40 MHz main clock
; Timer rate
TDDR
PRD
;
80 kHz
9
24 (18h)
;
50 kHz
9
39 (27h)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ
0018h
tcr_val.equ
0029h
splk
#0000h, temp
; clear timer
out
temp, TIM
splk
#prd_val, temp
; set PRD
out
temp, PRD
splk
#tcr_val, temp
; set TDDR, and TRB=1 for auto-reload
out
temp, TCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0
CS
– and set high
; IO1
LDAC
– and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
in
temp, ASPCR
; configure as output
lacl
temp
or
#0003h
sacl
temp
out
temp, ASPCR
in
temp, IOSR
; set them high
lacl
temp
or
#0003h
sacl
temp
out
temp, IOSR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1
Transmit mode – generate FSX
; SSPCR.MCM=1
Clock mode – internal clock source
; SSPCR.FSM=1
Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
splk
#0000Eh, temp
out
temp, SSPCR
; reset transmitter
splk
#0002Eh, temp
out
temp, SSPCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
lacl
#000h
sacl r_ptr
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
clrc
INTM
; enable maskable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
next
idle
;wait for interrupt
b
next
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; all else fails stop here
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done
b
done
;hang there
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