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參數資料
| 型號： | TLV5606IDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 22/27頁 |
| 文件大小： | 636K |
| 代理商： | TLV5606IDR |
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TLV5606
2.7V TO 5.5V LOW POWER 10BIT DIGITALTOANALOG
CONVERTERS WITH POWER DOWN
SLAS259B DECEMBER 1999 REVISED APRIL 2004
4
WWW.TI.COM
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications RL = 10 k, CL = 100 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
bits
INL
Integral nonlinearity
See Note 4
± 0.5
±1.5
LSB
DNL
Differential nonlinearity
See Note 5
± 0.2
± 1
LSB
EZS
Zero-scale error (offset error at zero scale)
See Note 6
±10
mV
Zero-scale-error temperature coefficient
See Note 7
10
ppm/
°C
EG
Gain error
See Note 8
±0.6
% of
FS
voltage
Gain-error temperature coefficient
See Note 9
10
ppm/
°C
NOTES:
4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 1023.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code. Tested from code 10 to code 1023.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) EZS (Tmin)]/Vref × 106/(Tmax Tmin).
8. Gain error is the deviation from the ideal output (2Vref 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) EG (Tmin)]/Vref × 106/(Tmax Tmin).
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 k
0
AVDD0.1
V
Output load regulation accuracy
RL = 2 k, vs 10 k
0.1
±0.25
% of FS
voltage
reference input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
0
VDD1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc
Slow
525
kHz
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc
Fast
1.3
MHz
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
75
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = VDD
±1
A
IIL
Low-level digital input current
VI = 0 V
±1
A
CI
Input capacitance
3
pF
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