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參數資料
| 型號： | TLV5610IYZR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20 |
| 封裝： | GREEN, WCSP-20 |
| 文件頁數： | 9/14頁 |
| 文件大小： | 180K |
| 代理商： | TLV5610IYZR |
www.ti.com
1
3
16
X
D15
D14
D13
D12
D1
X
SCLK
DIN
X
D15
(1)
D14
(1)
D13
(1)
D12
(1)
D1
(1)
X
DOUT
X
t
wH
t
wL
t
su(D)
t
h(D)
FS
( CMode)
m
FS
(DSPMode)
t
wH(FS)
t
wL(FS)
t
su(FS
CK)
-
t
su(C16
FS)
-
D0
(1)
17
t
su(FS
C17)
-
t
su(CK
FS)
-
NOTE:(1)Previousinputdata.
2
4
twL(LDAC)
LDAC
OUTx
ts
±0.5LSB
DIGITAL INPUT TIMING REQUIREMENTS
SBAS389A – JULY 2006 – REVISED JULY 2006
Figure 1. Serial Interface Timing
Figure 2. Output Timing
PARAMETER
MIN
TYP
MAX
UNIT
tsu(FS-CK)
Setup time, FS low before next negative SCLK edge
8
ns
Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising edge
tsu(C16-FS)
10
ns
of FS. C mode only
tsu(FS-C17)
C mode, setup time, FS high before 17th positive SCLK.
10
ns
tsu(CK-FS)
DSP mode, setup time, SLCK low before FS low.
5
ns
twL(LDAC)
LDAC duration low
10
ns
twH
SCLK pulse duration high
16
ns
twL
SCLK pulse duration low
16
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
FS duration high
10
ns
twL(FS)
FS duration low
10
ns
ts
Settling time
4
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