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參數(shù)資料
型號(hào)： TLV5616CDRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, PDSO8
封裝： GREEN, PLASTIC, SOIC-8
文件頁(yè)數(shù)： 24/28頁(yè)
文件大小： 698K
代理商： TLV5616CDRG4
TLV5616C, TLV5616I
2.7V TO 5.5V LOW POWER 12BIT DIGITALTOANALOG
CONVERTERS WITH POWER DOWN
SLAS152D DECEMBER 1997 REVISED APRIL 2004
5
WWW.TI.COM
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ts(FS)
Output settling time, full scale
RL = 10 k,
CL = 100 pF,
Fast
3
5.5
s
ts(FS)
Output settling time, full scale
RL = 10 k,
See Note 11
CL = 100 pF,
Slow
9
20
s
ts(CC)
Output settling time, code to code
RL = 10 k,
CL = 100 pF,
Fast
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,
See Note 12
CL = 100 pF,
Slow
2
s
SR
Slew rate
RL = 10 k,
CL = 100 pF,
Fast
3.6
V/ s
SR
Slew rate
RL = 10 k,
See Note 13
CL = 100 pF,
Slow
0.9
V/
s
Glitch energy
Code transition from 0x7FF to 0x800
10
nVs
S/N
Signal to noise
fs = 400 KSPS
fout = 1.1 kHz,
74
dB
S/(N+D)
Signal to noise + distortion
fs = 400 KSPS
fout = 1.1 kHz,
RL = 10 k
CL = 100 pF,
66
dB
THD
Total harmonic distortion
RL = 10 k,
CL = 100 pF,
BW = 20 kHz
68
dB
Spurious free dynamic range
BW = 20 kHz
70
dB
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CSFS)
Setup time, CS low before FS
↓
10
ns
tsu(FSCK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
Pulse duration, SCLK high
25
ns
twL
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
Pulse duration, FS high
20
ns
相關(guān)PDF資料
PDF描述
TLV5616IDGKG4 SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, PDSO8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV5616CP 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
TLV5616CPE4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7-5.5 V Low Power 12-Bit RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
TLV5616I 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5616ID 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
TLV5616IDG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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