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參數(shù)資料
| 型號： | TLV5617AIDG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 468K |
| 代理商： | TLV5617AIDG4 |
TLV5617A
2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS234F – JULY 1999 – REVISED JULY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD
Power supply current
No load,
All inputs = AGND or VDD,
Fast
1.6
2.5
mA
IDD
Power supply current
No load,
All in uts
AGND or VDD,
DAC latch
0x800
mA
IDD
Power su
ly current
DAC latch = 0x800
Slow
06
1
mA
DAC latch = 0x800
Slow
0.6
1
Power down supply current
1
A
PSRR
Power supply rejection ratio
Zero scale, See Note 2
–65
dB
PSRR
Power supply rejection ratio
Full scale, See Note 3
–65
dB
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
bits
INL
Integral nonlinearity
See Note 4
±0.7
±1
LSB
DNL
Differential nonlinearity
See Note 5
±0.1
±0.5
LSB
EZS
Zero-scale error (offset error at zero scale)
See Note 6
±12
mV
EZS TC
Zero-scale-error temperature coefficient
See Note 7
3
ppm/
°C
E
Gain error
See Note 8
VDD = 2.7 V to 3.3 V
±0.6
% full
EG
Gain error
See Note 8
VDD = 4.5 V to 5.5 V
±0.29
% full
scale V
EG TC
Gain-error temperature coefficient
See Note 9
1
ppm/
°C
NOTES:
4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.
5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/2Vref × 106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k.
9. Gain temperature coefficient is given by: EG TC = [EG (Tmax) – Eg (Tmin)]/2Vref × 106/(Tmax – Tmin).
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage range
RL = 10 k
VDD–0.4
V
Output load regulation accuracy
VO = 4.096 V, 2.048 V, RL = 2 k to 10 k
±0.1
% FS
reference input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
0
VDD–1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference input bandwidth
REF=0 2V
+1 024Vdc
Fast
1.3
MHz
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Slow
525
kHz
Reference feedthrough
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
– 80
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
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| TLV5617AIDR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 10-Bit 2.5 us Dual DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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| TLV5618A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
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