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參數資料
| 型號： | TLV5620IN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-14 |
| 文件頁數： | 13/14頁 |
| 文件大小： | 180K |
| 代理商： | TLV5620IN |
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level input current
VI = VDD
±10
A
IIL
Low-level input current
VI = 0 V
±10
A
IO(sink)
Output sink current
Each DAC output
20
A
IO(source)
Output source current
Each DAC output
1
mA
Ci
Input capacitance
15
pF
Ci
Reference input capacitance
15
pF
IDD
Supply current
VDD = 3.3 V
2
mA
Iref
Reference input current
VDD = 3.3 V, Vref = 1.5 V
±10
A
EL
Linearity error (end point corrected)
Vref = 1.25 V, × 2 gain, See Note 1
±1
LSB
ED
Differential linearity error
Vref = 1.25 V, × 2 gain, See Note 2
±0.9
LSB
EZS
Zero-scale error
Vref = 1.25 V, × 2 gain, See Note 3
0
30
mV
Zero-scale error temperature coefficient
Vref = 1.25 V, × 2 gain, See Note 4
10
V/°C
EFS
Full-scale error
Vref = 1.25 V, × 2 gain, See Note 5
±60
mV
Full-scale error temperature coefficient
Vref = 1.25 V, × 2 gain, See Note 6
±25
V/°C
PSRR
Power-supply sensitivity
See Notes 7 and 8
0.5
mV/V
NOTES:
1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 k.
6. Full-scale error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin).
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect
of this signal on the zero-code output voltage.
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of
this signal on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output slew rate
CL = 100 pF
RL = 10 k
1
V/
s
Output settling time
To
±0.5 LSB, CL = 100 pF, RL = 10 k, See Note 9
10
s
Large-signal bandwidth
Measured at – 3 dB point
100
kHz
Digital crosstalk
CLK = 1-MHz square wave measured at DACA-DACD
–50
dB
Reference feedthrough
See Note 10
–60
dB
Channel-to-channel isolation
See Note 11
–60
dB
Reference input bandwidth
See Note 12
100
kHz
NOTES:
9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within
± 0.5 LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 VPP at 10 kHz.
12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 VPP and with a digital input code of full-scale.
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