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參數資料
| 型號： | TLV5624IDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 3/22頁 |
| 文件大小： | 571K |
| 代理商： | TLV5624IDR |
TLV5624
2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235B JULY 1999 REVISED APRIL 2004
11
WWW.TI.COM
APPLICATION INFORMATION
serial interface (continued)
TMS320
DSP
XF0
CLKX
DX
FSX
XF1
TLV5624
CS
FS
DIN SCLK
TLV5624
CS
FS
DIN
SCLK
Figure 13. TMS320 Interface
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows
an example of how to connect the TLV5624 to TMS320, SPI
or Microwire using only three pins.
TMS320
DSP FSX
CLKX
DX
TLV5624
SCLK
DIN
FS
SPI
I/O
SCK
MOSI
TLV5624
SCLK
DIN
FS
Microwire
I/O
SK
SO
TLV5624
SCLK
DIN
FS
CS
Figure 14. Three-Wire Interface
Notes on SPI
and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI
and Microwire), two write
operations must be performed to program the TLV5624. After the write operation(s), the DAC output is updated
automatically on the next positive clock edge following the 16th falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax +
1
t
whmin ) twlmin
+ 20 MHz
The maximum update rate is:
f
updatemax +
1
16 t
whmin ) twlmin
+ 1.25 MHz
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5624 has to be considered, too.
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