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參數(shù)資料
型號: TLV5627CDR
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 8-BIT DAC, PDSO16
封裝: GREEN, PLASTIC, SOIC-16
文件頁數(shù): 8/23頁
文件大小: 462K
代理商: TLV5627CDR
TLV5627C, TLV5627I
2.7V TO 5.5V 8BIT 4CHANNEL DIGITALTOANALOG CONVERTERS
WITH POWER DOWN
SLAS232A JUNE1999 REVISED JULY 2002
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies (continued)
The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well-managed and there are negligible voltage drops across the ground plane.
A 0.1-
F ceramic-capacitor bypass should be connected between VDDand AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 20 shows the ground plane layout and bypassing technique.
0.1
F
Analog Ground Plane
1
2
3
4
8
7
6
5
Figure 20. Power-Supply Bypassing
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