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參數資料
| 型號： | TLV5627IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 8-BIT DAC, PDSO16 |
| 封裝： | GREEN, PLASTIC, SOIC-16 |
| 文件頁數： | 17/21頁 |
| 文件大小： | 293K |
| 代理商： | TLV5627IDRG4 |
TLV5627C, TLV5627I
2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS232A – JUNE1999 – REVISED JULY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output
RL = 10 k
0
AVDD–0.4
V
Output load regulation accuracy
RL = 2 k vs 10 k
0.1
0.25
% of FS
voltage
reference input (REFINAB, REFINCD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
See Note 8
0
AVDD–1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 9)
–75
dB
Reference input bandwidth
REFIN = 0 2 V
+ 1 024 V dc
Slow
0.5
MHz
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc
Fast
1
MHz
NOTES:
8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = DVDD
±1
A
IIL
Low-level digital input current
VI = 0 V
±1
A
CI
Input capacitance
3
pF
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5V supply No load Clock running
Slow
1.4
2.2
mA
IDD
Power supply current
5-V supply, No load, Clock running
Fast
3.5
5.5
mA
IDD
Power supply current
3V supply No load Clock running
Slow
1
1.5
mA
3-V supply, No load, Clock running
Fast
3
4.5
mA
Power down supply current, See Figure 12
1
A
PSRR
Power supply rejection ratio
Zero scale gain
See Notes 10 and 11
– 68
dB
PSRR
Power supply rejection ratio
Gain
See Notes 10 and 11
– 68
dB
10. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
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