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參數(shù)資料
型號(hào): TLV5636IDRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO8
封裝: GREEN, PLASTIC, MS-012AA, SOIC-8
文件頁數(shù): 4/23頁
文件大小: 521K
代理商: TLV5636IDRG4
www.ti.com
TMS320
DSP FSX
CLKX
DX
TLV5636
SCLK
DIN
FS
SPI
I/O
SCK
MOSI
TLV5636
SCLK
DIN
FS
Microwire
I/O
SK
SO
TLV5636
SCLK
DIN
FS
CS
SERIAL CLOCK AND UPDATE RATE
f
sclkmax +
1
t
whmin ) twlmin
+ 20 MHz
(1)
f
updatemax +
1
16 t
whmin ) twlmin
+ 1.25 MHz
(2)
DATA FORMAT
TLV5636
SLAS223C – JUNE 1999 – REVISED APRIL 2004
APPLICATION INFORMATION (continued)
Figure 14. Three Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be
performed to program the TLV5636. After the write operation(s), the DAC output is updated automatically on the
next positive clock edge following the sixteenth falling clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5636 has to be considered, too.
The 16-bit data word for the TLV5636 consists of two parts:
Program bits (D15..D12)
New data (D11..D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R1
SPD
PWR
R0
12 Data bits
SPD
: Speed control bit
1 = fast mode
0 = slow mode
PWR
: Power control bit
1 = power down
0 = normal operation
The following table lists the possible combination of the register select bits:
Register Select Bits
R1
R0
REGISTER
0
Write data to DAC
0
1
Reserved
1
0
Reserved
1
Write data to control register
12
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