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參數(shù)資料
| 型號(hào)： | TLV5637CDG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 2/21頁(yè) |
| 文件大?。?/td> | 422K |
| 代理商： | TLV5637CDG4 |
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APPLICATION INFORMATION
GENERAL FUNCTION
2 REF
CODE
0x1000
[V]
SERIAL INTERFACE
TMS320
DSP FSX
CLKX
DX
TLV5637
SCLK
DIN
CS
SPI
I/O
SCK
MOSI
TLV5637
SCLK
DIN
CS
Microwire
I/O
SK
SO
TLV5637
SCLK
DIN
CS
SERIAL CLOCK FREQUENCY AND UPDATE RATE
f
sclkmax =
1
(t
+t
)
whmin
wlmin
=20MHz
f
=
updatemax
1
16(t
+t
)
whmin
wlmin
=1.25MHz
SLAS224C – JUNE 1999 – REVISED JUNE 2007
The TLV5637 is a dual 10-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. Because
it is a 10-bit DAC, only D11 to D2 are used. D0 and D1 are ignored. A power-on reset initially puts the internal
latches to a defined state (all bits zero).
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5637 to TMS320, SPI, and Microwire.
Figure 13. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5637. After the write operation(s), the holding registers or the control register
are updated automatically on the 16th positive clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5637 has to be considered as well.
10
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