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參數資料
| 型號： | TLV5637IDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 18/21頁 |
| 文件大小： | 422K |
| 代理商： | TLV5637IDR |
www.ti.com
ELECTRICAL CHARACTAERISTICS (CONTINUED)
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
CS
DIN
D15
D14
D13
D12
D1
D0
X
1
X
2
3
4
5 15
16
X
twH
tsu(D)
th(D)
tsu(CS-CK)
tsu(C16-CS)
SLAS224C – JUNE 1999 – REVISED JUNE 2007
over recommended operating conditions (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Fast
0.8
2.4
ts(FS)
Output settling time, full scale
RL = 10k, CL = 100pF,
See (1)
s
Slow
2.8
5.5
Fast
0.4
1.2
ts(CC)
Output settling time, code to code
RL = 10k, CL = 100pF,
See (2)
s
Slow
0.8
1.6
Fast
12
SR
Slew rate
RL = 10k, CL = 100pF,
See (3)
V/s
Slow
1.8
Glitch energy
DIN = 0 to 1, fCLK = 100kHz,
CS = VDD
5
nV-S
SNR
Signal-to-noise ratio
53
56
S/(N+D)
Signal-to-noise + distortion
50
54
fs = 480kSPS, fout = 1kHz, RL = 10k, CL = 100pF
dB
THD
Total harmonic distortion
61
50
SFDR
Spurious free dynamic range
51
62
(1)
Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of
0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.
(2)
Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one
count. Not tested, assured by design.
(3)
Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
MIN
NOM
MAX
UNIT
tsu(CS-CK)
Setup time, CS low before first negative SCLK edge
10
ns
tsu(C16-CS)
Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge
10
ns
twH
SCLK pulse width high
25
ns
twL
SCLK pulse width low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
10
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
Figure 1. Timing Diagram
6
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