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參數(shù)資料
| 型號(hào)： | TLV571IPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | GREEN, PLASTIC, TSSOP-24 |
| 文件頁(yè)數(shù)： | 23/28頁(yè) |
| 文件大小： | 479K |
| 代理商： | TLV571IPWG4 |
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TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
control registers
0:
Binary
1:
2’s
Complement
0:
Reserved
Bit,
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
STARTSEL
A1
A0
D4
D3
D2
D1
D0
D5
Control Register Zero (CR0)
D4
D5
D3
D2
D1
D0
PROGEOC
CLKSEL
SWPWDN
Don’t Care
0:
HARDWARE
START
(CSTART)
A(1:0)=00
1:
SOFTWARE
START
0:
INT
1:
EOC
0:
Internal
Clock
1:
External
Clock
0:
NORMAL
1:
Powerdown
Reserved
Control Register One (CR1)
D4
D5
D1
D0
OSCSPD
0 Reserved 0 Reserved
OUTCODE
Reserved
0:
Reserved
Bit
Always
Write 0
A(1:0)=01
0:
Reserved
Bit
Always
Write 0
D3
D2
Don’t Care
0:
Reserved
Bit,
Always
Write 0
Figure 2. Input Data Format
hardware configuration option
The TLV571 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RD
signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.
The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardware
start of conversion using CSTART.
ADC conversion modes
The TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.
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