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參數資料
| 型號： | TLV62065DSGT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING REGULATOR, 3400 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 2 X 2 MM, 0.75 MM HEIGHT, PLASTIC, WSON-8 |
| 文件頁數： | 10/26頁 |
| 文件大小： | 1182K |
| 代理商： | TLV62065DSGT |
I
RMSCout + Vout
1 *
Vout
Vin
L
1
2
3
SLVSAC4 – NOVEMBER 2010
www.ti.com
In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter,
the output capacitor COUT need to be decreased in order not to exceed the recommended effective capacitance
range. In this case a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
(3)
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a 10F ceramic capacitor is recommended. The input capacitor can be
increased without any limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 3. List of Capacitors
CAPACITANCE
TYPE
SIZE [ mm3]
SUPPLIER
10mF
GRM188R60J106M
0603: 1.6 x 0.8 x 0.8
Murata
22mF
GRM188R60G226M
0603: 1.6 x 0.8 x 0.8
Murata
22F
CL10A226MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
10F
CL10A106MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signal
Switching node, SW
Inductor current, IL
Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter
combinations. As a next step in the evaluation of the regulation loop, the load transient response is tested. The
time between the application of the load transient and the turn on of the P-channel MOSFET, the output
capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to
ΔI(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO
generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are
most easily interpreted when the device operates in PWM mode at medium to high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
18
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s) :TLV62065
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