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參數資料
| 型號： | TLV990-40PFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 8/24頁 |
| 文件大小： | 418K |
| 代理商： | TLV990-40PFB |
TLV99040
3V, 10BIT, 40MSPS AREA CCD ANALOG FRONT END
SLAS326A JANUARY 2001 REVISED MARCH 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
REGISTER DEFINITION
test register format
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TB9
TB8
TB7
TB6
X
TB3
TB2
X
Default register value =0110000000
These bits must be set to 1011 for 40 MSPS
test register description
BIT
NAME
DESCRIPTION
D9D6
TB9TB6
These four bits are used to program internal DC bias current. The bias current programming uses the following equation:
Ibias = 8 A + (code) × 2 A
Hence, Ibias varies from 8 A (code=0000) to 38 A (code=1111), with a linear step of 2 A.
Default code is 0110. These bits must be set to 1011 for 40 MSPS
D5, D4
Reserved
D3
TB3
1 – use external reference, power down internal reference
0 – use internal reference (default)
D2
TB2
This bit selects test input mode.
0 Single-ended input on CCDIN pin,
1 Differential input on both CCDIN and VIDEOIN pins
D1, D0
Reserved
PRINCIPLES OF OPERATION
CCD mode operation
The output from the CCD sensor is first fed to a correlated double sampler (CDS) through the CCDIN pin. The
CCD signal is sampled and held during the reset reference interval and the video signal interval. By subtracting
two resulting voltage levels, the CDS removes low frequency noise from the output of the CCD sensor and
obtains the voltage difference between the CCD reference level and the video level of each pixel. Two
sample/hold control pulses (SR and SV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLV990-40. The ac-coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLCCD input. The bias at the input to the TLV990-40 is
set to 1.2 V. Normally, CLCCD is applied at sensor’s line rate. A capacitor, with a value ten times larger than
that of the input ac-coupling capacitor, should be connected between the CLREF pin and the AGND.
When operating the TLV990-40 at its maximum speed, the CCD internal source resistance should be smaller
than 50
. Otherwise CCD output buffering is required.
The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 to 36 dB
by programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit resolution
on a linear dB scale, resulting in a 0.045-dB gain step. The gain can be expressed by the following equation,
Gain = PGA code
× 0.045 dB
Where PGA code has a range of 0 to 767.
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| TLV990-40PFBG4 | 功能描述:視頻模擬/數字化轉換器集成電路 3-V 10-Bit 40 MSPS Area CCD RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數量:1 ADC 輸入端數量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TLV990B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR |
| TLV990BPFB | 功能描述:IC CCD SIGNAL PROC/DGTZR 48TQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:- 通道數:2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| TLV990PFB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR |
| TLVAIC12KIRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Mono Voice Band CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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