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參數資料
| 型號： | TMC2243 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10 x 10 Bit, 20 MHz CMOS FIR(Finite Impulse Response) Filter(10 x 10 位,20 MHz CMOS 有限脈沖響應濾波器) |
| 中文描述： | 10 × 10位，20兆赫的CMOS FIR（有限沖擊響應）濾波器（10 × 10位，20兆赫的CMOS有限脈沖響應濾波器） |
| 文件頁數： | 1/16頁 |
| 文件大小： | 120K |
| 代理商： | TMC2243 |
www.fairchildsemi.com
Features
20 MHz data input and computation rate
10 x 10 bit multiplication with 23-bit extended precision
sum of products (overflow, plus 16 output and 6 guard
bits)
Up to 3 zero and 3 non-zero stages per device
Two’s complement arithmetic
16-bit Sum-In and Sum-Out ports for cascading
Internal 1/2 LSB rounding
All inputs and outputs are registered
One coefficient update per clock cycle
Low power consumption CMOS process
Single +5V supply
Available in 68-pin ceramic pin grid array and 69-pin
plastic PGA packages
Applications
FIR filters
Adaptive filters
Multi-bit correlation
One and two dimension video filtering
Radar signal processors
One and two dimension convolution
Arithmetic element for systolic array processors
Description
The TMC2243 is a video speed three stage 10 x 10 bit FIR
(Finite Impulse Response) filter integrated circuit composed
of three registered multiplier-adders concatenated into a one-
dimensional systolic array. Utilizing two’s complement rep-
resentation, the TMC2243 accepts one 10-bit data point,
updates one 10-bit coefficient, and produces one 16-bit
rounded, filtered output point every 50 nanoseconds.
The TMC2243 has features which facilitate longer FIR fil-
ters: a 16-bit SUM-In port and user programmable pipeline
registers. Enabling these registers allows the insertion of a
zero-coefficient stage before each regular filter stage for up
to six stages per TMC2243. Larger FIR filters can be built by
cascading Sum-In and Sum-Out.
Coefficients are stored in 3 registers and are addressed via
the 2-bit Write Enable control, allowing one coefficient to be
changed per clock cycle. All Data, Sum-In, Sum-Out and
instruction inputs are registered on the rising edge of clock.
The 16 bits below the MSB of the 23-bit internal summation
path are available at the SUM-In and Sum-Out ports. Six bits
of cumulative word growth are provided internally. Data
Overflow is indicated by an output flag.
T MC2243
CMOS FIR Filter
10 x 10 Bit, 20 MHz
Block Diagram
10
Decoder
10
10
10
2
10
10
16
16
OV
16
17
23
1000002
23
OE
65-2243-01
10
10
20
6
6 (LSB)
LSB’s
20
20
CI9-0
DI9-0
SI21-6
CLK
TO ALL REGISTERS
FT1
FT2
SO21-6
FT3
CWE1-0
C1
C2
C3
Rev. 1.1.1
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