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參數資料
| 型號： | TMC2601R2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 7/12頁 |
| 文件大小： | 49K |
| 代理商： | TMC2601R2C |
TMC2601
PRODUCT SPECIFICATION
4
Pr
eliminar
y
Infor
mation
Functional Description
The TMC2601 serializer is a CMOS integrated circuit which
converts parallel data in a format such as SMPTE125M or
SMPTE244M into a serial format, such as SMPTE 259M. It
encodes 8- or 10-bit TTL-compatible parallel signals into
serial differential pseudo-ECL signals at up to 370Mb/s. It
operates from a single 5V supply and is packaged in a 44-pin
PLCC.
The internal functional blocks include the sync detector, data
serializer, polynomial scrambler and NRZ to NRZI con-
verter, and 10-fold clock frequency multiplier.
Sync Detector
On each rising edge of PCKI, the Sync Detector looks for
combinations of all 1’s or all 0’s on pins DI9-2. Whenever it
encounters one of these combinations, the Sync Detector
drives SYNC DET low on the next parallel clock cycle. If
control SYNC DET DIS is low, it also overrides DI1-0 to
match DI9-2, such that 000 through 003 (hex) become 000,
and 3FC through 3FF become 3FF, to comply with
SMPTE259.
Polynomial Scrambler
This feedback shift register pseudorandomizes the incoming
data, using the SMPTE-specied xed polynomial X9 + X4
+1, thereby minimizing the DC component in the output
stream. A second polynomial operator, cascaded with the
rst and based on X+1, converts NRZ data into NRZI, turn-
ing any long sequences of 1’s into series of transitions. When
high, control SSS bypasses these two blocks, allowing direct
serialization of the incoming data.
Phase-Locked Loop
The PLL, which multiplies the clock frequency by 10, com-
prises a phase detector, a charge pump, a loop lter, a VCO,
and a divide-by-ten counter. On each parallel clock cycle, the
loop lter receives a charge proportional to the phase error
and perturbs the VCO’s frequency appropriately.
VCO Frequency Selector
The chip provides four nominal frequency ranges, selected
by FS1-0, as follows:
The lock detect circuit disables the serial data output when
the loop is not locked, at which time the Lock Detect ag
will be low.
Complementary serial data emerge on SDO and SDO,
whereas the serial clock appears on SCK and SCK. To
reduce system noise and to save power, user not needing the
serial clock may disable it by grounding LOOPF/SCKDIS.
The chip also provides a single-ended ECL parallel clock
output, PCKO, regenerated from the internal PLL.
FS0
FS1
Nominal Frequency (MHz)
0
270 (D1)
0
1
360
1
0
143 (NTSC D2)
1
177 (PAL D2)
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