
www.fairchildsemi.com
REV. 1.0.1 5/9/00
Features
32-bit by 16-bit fixed-point integer division with 32-bit
quotient
20 MHz clock rate and pipelined throughput rate
Three-bus I/O architecture allows unrestricted throughput
Easy system interfacing
Status flags for divide-by-zero and inexact result
All inputs and outputs TTL compatible
Applications
Graphics and image processors
Matrix operations and geometric transforms
Perspective extraction
Radar signal processing
Range scaling
Description
The TMC3211 is a fast monolithic two’s complement integer
divider which can divide a 32-bit dividend by a 16-bit divisor
to produce a 32-bit quotient, with a maximum pipelined
throughput of 20 MOPS (Million Operations Per Second).
Data is input on separate busses, and quotients are available
on a 32-bit output bus with synchronous three-state enable.
All data inputs and outputs are registered and TTL compati-
ble. All input and output signal timing is referenced to the
rising edge of Clock.
The TMC3211 has a single system clock and separate load
enable controls for the dividend and divisor registers. This
allows the device to be used in applications requiring divi-
sion by a constant. Underflow automatically produces the
expected zero quotient, and dividing by zero sets a divide-
by-zero output flag.
The internal architecture of the TMC3211 allows all 32-bit
two’s complement integer dividends and nonzero 16-bit
two’s complement integer divisors, without prenormaliza-
tion. The output quotient format is 32-bit integer.
The TMC3211 makes a full-precision, full-speed divide
function available to designers of workstations, image
processors, and radar systems who need to perform
perspective extractions, matrix operations, range scaling, and
other complex functions.
Block Diagram
ENX
ENY
CLK
OE
20
19
2-18
1
16
16
32
32
Quotients
Divisor
Dividend
16 - Stage
Non-Restoring
Divider
32
Flags
32
32
2
X
15-0
X
31-0
Q
31-0
DZERO, INX
T MC3211
Integer Divider
32-Bit, 20 MOPS