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參數(shù)資料
| 型號： | TMDS261PAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 7/43頁 |
| 文件大小： | 2160K |
| 代理商： | TMDS261PAG |
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
www.ti.com............................................................................................................................................................................................ SLLS953 – DECEMBER 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Single-ended HIGH-level output voltage
AVCC = 3.3 V, RT = 50
AVCC – 10
AVCC + 10
mV
VOL
Single-ended LOW-level output voltage
AVCC – 600
AVCC – 400
mV
VSWING
Single-ended output voltage swing
400
600
mV
Change in steady-state common-mode
VOC(SS)
5
mV
output voltage between logic states
VOD(pp)
Peak-to-peak output differential voltage
800
1200
mV
V(O)SBY
Single-ended standby output voltage
AVCC – 10
AVCC + 10
mV
0 V
≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
I(O)OFF
Single-ended power-down output current
–10
10
A
RT = 50
IOS
Short-circuit output current
See Figure 16
-15
12
15
mA
VCD(pp)
Minimum valid clock differential voltage
Input TMDS clock frequency = 300
100
mV
(peak-to-peak)
MHz
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
tPLH
Propagation delay time
250
800
ps
tPHL
Propagation delay time
250
800
ps
tR1
Rise time, fastest mode (default setting):
84
110
140
ps
Fastest Setting
tF1
Fall time, fastest mode (default setting):
84
110
140
ps
Fastest Setting
tR2
Rise time, fastest mode + 50 ps
142
160
190
ps
(approximately)
tF2
Fall time, fastest mode + 50 ps
142
160
190
ps
(approximately)
tR3
Rise time, fastest mode + 100 ps
187
210
230
ps
(approximately)
tF3
Fall time, fastest mode + 100 ps
187
210
230
ps
(approximately)
tR4
Rise time, fastest mode + 120 ps
216
230
260
ps
(approximately): Slowest Setting
tF4
Fall time, fastest mode + 120 ps
216
230
260
ps
(approximately): Slowest Setting
tSK(P)
Pulse skew (see (2))
8
15
ps
tSK(D)
Intra-pair skew
10
30
ps
tSK(O)
Inter-pair skew (see (3))
100
ps
tJITD(PP)
Peak-to-peak output residual data jitter
AVCC = 3.3 V, RT = 50 , dR = 2.25 Gbps.
40
88
ps
See Figure 14 for measurement setup;
residual jitter is the total jitter measured at
TTP4 minus the jitter measured at TTP1. See
Figure 15 for the loss profile of the cable used
input TMDS data rate.
(1)
All typical values are at 25°C and with a 3.3-V supply.
(2)
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
(3)
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
Copyright 2008, Texas Instruments Incorporated
15
Product Folder Link(s) :TMDS261
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