- 您現在的位置：買賣IC網 > PDF目錄382646 > TMJ320C6211GGP167 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSORS PDF資料下載
參數資料
| 型號： | TMJ320C6211GGP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 36/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMJ320C6211GGP167 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Table 20. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15
10)
POWER-DOWN
MODE
WAKE-UP METHOD
EFFECT ON CHIP’S OPERATION
000000
No power-down
—
—
001001
PD1
Wake by an enabled interrupt
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
Power down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
010001
PD1
Wake by an enabled or
non-enabled interrupt
011010
PD2
Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
011100
PD3
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
—
All others
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
Reserved
—
相關PDF資料 |
PDF描述 |
|---|---|
| TMX320C6201GGP167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6211GJC167 | TRIMMER, 1K |
| TMJ320C6211GJC167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6201GJC167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211GNY167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMJ320C6211GHK167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMJ320C6211GJC167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMJ320C6211GJL167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMJ320C6211GLS167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMJ320C6211GLW167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
發布緊急采購，3分鐘左右您將得到回復。