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參數(shù)資料
| 型號(hào)： | TMJ320C6211GHK167 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁(yè)數(shù)： | 33/83頁(yè) |
| 文件大小： | 1176K |
| 代理商： | TMJ320C6211GHK167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
clock PLL (continued)
CLKMODE0
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
P
Internal to
C6211/C6211B
CPU
CLOCK
P
1
0
3.3V
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
DD
.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
Table 19. C6211/C6211B PLL Component Selection
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
65
167
CLKOUT2
RANGE
(MHz)
R1 [
±
1%]
(
)
C1 [
±
10%]
(nF)
C2 [
±
10%]
(pF)
TYPICAL
LOCK TIME
(
μ
s)
x4
16.3
41.6
32.5
83
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
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