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參數(shù)資料
| 型號(hào)： | TMJ320C6211GLS167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 52/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMJ320C6211GLS167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles
(see Figure 22)
NO.
C6211
150
C6211
167
C6211BGFNA
150
C6211B
150
C6211B
167
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
6
t
su(EDV-EKOH)
Setup time, read EDx valid before
ECLKOUT high
2.5
2.5
2.5
ns
7
t
h(EKOH-EDV)
Hold time, read EDx valid after
ECLKOUT high
1
2.5
2
ns
The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM
cycles
(see Figure 22
Figure 28)
NO.
PARAMETER
C6211
150
C6211
167
C6211BGFNA
150
C6211B
150
C6211B
167
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
1
t
d(EKOH-CEV)
Delay time, ECLKOUT high to CEx
valid
1.5
6.5
1
6.5
1.2
6.5
ns
2
t
d(EKOH-BEV)
Delay time, ECLKOUT high to BEx
valid
6.5
6.5
6.5
ns
3
t
d(EKOH-BEIV)
Delay time, ECLKOUT high to BEx
invalid
1.5
1
1.2
ns
4
t
d(EKOH-EAV)
Delay time, ECLKOUT high to EAx
valid
6.5
6.5
6.5
ns
5
t
d(EKOH-EAIV)
Delay time, ECLKOUT high to EAx
invalid
1.5
1
1.2
ns
8
t
d(EKOH-CASV)
Delay time, ECLKOUT high to
ARE/SDCAS/SSADS valid
1.5
6.5
1
6.5
1.2
6.5
ns
9
t
d(EKOH-EDV)
Delay time, ECLKOUT high to EDx
valid
7
7
7
ns
10
t
d(EKOH-EDIV)
Delay time, ECLKOUT high to EDx
invalid
1.5
1
1.2
ns
11
t
d(EKOH-WEV)
Delay time, ECLKOUT high to
AWE/SDWE/SSWE valid
1.5
6.5
1
6.5
1.2
6.5
ns
12
t
d(EKOH-RAS)
Delay time, ECLKOUT high to
AOE/SDRAS/SSOE valid
1.5
6.5
1
6.5
1.2
6.5
ns
The C6211/C6211B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
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