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參數(shù)資料
| 型號： | TMP141AIDBVTG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 662K |
| 描述： | IC TEMP SENSOR DGTL OUT SOT23-6 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | SensorPath™ |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -40°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓?fù)洌?/td> | ADC（三角積分型），寄存器庫 |
| 輸出類型： | 1 線 SensorPath? |
| 輸出警報： | 無 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
TMP141
SBAS347A MARCH 2005 REVISED JULY 2006
www.ti.com
15
GLOSSARY
ACK (Acknowledge Bit): The bit that concludes a transmission indicating whether any errors were detected in the
transmission. A 1 indicates that no errors were found; a 0 indicates an error. An acknowledge error causes BER to be
set. BER will be set regardless of whether the device or the master generates the acknowledge error.
AT_E (Attention Enable): This is the LSB in the Temperature Control register (bit 0, register Ah). When set, the TMP141
will generate Attention Requests. If enabled, an Attention Request will be generated when a conversion is complete.
BER (Bus Error): A flag that is set when the TMP141 either generates or receives an Acknowledge error (bit 7 in the Status
register).
EN_S: (Sensor Enable Bit): This is bit 1 in the Temperature Control register. When set, temperature measurement is
enabled. Default setting is disabled. To report temperature, ENAB must also be set.
ENAB (Enable Temperature Sensing): This is a bit in the Device Control register. In the case of the TMP141, function
1 is temperature measurement. Setting this bit will enable temperature measurement (bit 4 in the Device Control register).
The sensor should also be turned on by the Sensor Enable flag (bit 1) in the Temperature Control register.
Even Parity: The number of bits in a transmission that are 1 is even. The SensorPath uses even parity. All bits after the
start bit (up to and including the parity bit) are included in this calculation, but the ACK bit is not.
ORUN (Overrun Error): This flag is set when a temperature conversion is completed before the previous conversion has
been read by the master (bit 4 in the Device Status register). If other conditions are met, overrun will generate an Attention
Request.
PCI SIG (assigned identifiers): The ID for Texas Instruments is 104Ch. This number is programmed into the Manufacturer
ID register. Other IDs can be fond at http://www.pcisig.com/membership/vid_search/. This number enables identification
of the device manufacturer (which can be useful in determining the features of a device) and to perform
manufacturer-specific operations. There are no vendor-specific operations for the TMP141all of the operations conform
to industry standards.
Pulse Width Encoding: A signaling scheme whereby the information is differentiated by the width of the pulse. In the case
of SensorPath, the pulses are created by pulling the bus low. The length of time that it is low determines the meaning of
that pulse. See the Digital Interface section on page 8.
SF1 (Status Function One): This flag is set when a temperature conversion is completed, and the data is stored in the
Readout register. It is reset when the master reads the temperature conversion, or when the TMP141 is reset.
Shutdown Mode: A very low-power state entered when the master writes to the shutdown bit (bit 1) in the Device Control
register. In the shutdown state, temperature conversions are stopped. The TMP141 consumes the lowest possible power
in this state (see also Low-Power Mode on page 11).
SWCLK: Single-Wire Clock, an optional signal used only when the SensorPath is used in synchronous mode. The TMP141
does not use and does not support this option. Systems that use SWCLK are using a two-wire SensorPath bus.
SWD (Single-Wire Data): The line used to communicate between master and slave devices as required by the specified
SensorPath. Five types of signals go over this line (Zero, One, Start, Attention Request, and Reset). Signals are
differentiated by the length of time that they hold the bus low. This is the only line used to communicate between the slaves,
such as the TMP141, and the master. A 1.25k& pull-up resistor may be integrated into the master, or it may be external.
Synchronous Mode: An optional mode used with SensorPath devices that do not meet the ?/SPAN>15% clock timing accuracy
requirement. The TMP141 clock meets the clock accuracy requirement, and therefore does not support the synchronous
mode (see SWCLK).
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