- 您現在的位置：買賣IC網 > PDF目錄382646 > TMP320C6202BPYP167 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSORS PDF資料下載
參數資料
| 型號： | TMP320C6202BPYP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 73/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMP320C6202BPYP167 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁當前第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
73
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
(see Figure 40)
NO.
150
167
UNIT
MASTER
MIN
26
4
SLAVE
MIN
2
6P
6 + 12P
MAX
MAX
4
5
t
su(DRV-CKXH)
t
h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0
(see Figure 40)
NO.
PARAMETER
150
167
UNIT
MASTER
§
MIN
L
9
T
9
9
SLAVE
MIN
MAX
L + 9
T + 9
MAX
1
2
3
t
h(CKXL-FXL)
t
d(FXL-CKXH)
t
d(CKXL-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
#
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit from
CLKX low
ns
ns
ns
9
6P + 4
10P + 20
6
t
dis(CKXL-DXHZ)
9
9
6P + 3
10P + 20
ns
7
t
d(FXL-DXV)
Delay time, FSX low to DX valid
H
9
H + 9
4P + 2
8P + 20
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
3
7
6
2
1
CLKX
FSX
DX
DR
5
Figure 40. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
相關PDF資料 |
PDF描述 |
|---|---|
| TMX320C6202BGHK167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6203BGHK167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGHK167 | MS3472W18-32P |
| TMP320C6202BGHK167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6202BGLW167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMP320C6202GFN100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6202GFNA100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6202GGP100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6202GGP120 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6202GGPA100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
發布緊急采購，3分鐘左右您將得到回復。