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參數(shù)資料
| 型號(hào)： | TMP320C6211PYP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 32/83頁(yè) |
| 文件大小： | 1176K |
| 代理商： | TMP320C6211PYP167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
clock PLL
All of the internal C62x
clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5
shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 6 shows the
external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C62x
device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise
and fall times should also be observed. For the input clock timing requirements, see the
input and output clocks
electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the
electrical characteristics over recommended
ranges of suppy voltage and operating case temperature
table and the
input and output clocks
electricals
section). Table 18 lists some examples of compatible CLKIN external clock sources.
Table 18. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER
MANUFACTURER
JITO-2
Fox Electronix
SaRonix Corporation
Epson America
Corning Frequency Control
Integrated Circuit Systems
Oscillators
STA series, ST4100 series
SG-636
342
MK1711-S, ICS525-02
PLL
Available Multiply Factors
CLKMODE0
PLL Multiply
Factors
CPU Clock
Frequency
f(CPUCLOCK)
1 x f(CLKIN)
4 x f(CLKIN)
0
1
x1(BYPASS)
x4
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
DD
.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
CLKMODE0
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
P
C2
Internal to
C6211/C6211B
CPU
CLOCK
C1
R1
3.3V
10 F
0.1 F
P
E
C3
C4
1
0
(For C1, C2, and R1 values, see Table 19.)
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