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參數資料
型號: TMP320C6413GTSA500
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數字信號處理器
文件頁數: 101/140頁
文件大小: 1958K
代理商: TMP320C6413GTSA500
Programmable Synchronous Interface Timing
101
April 2004
Revised May 2005
SPRS247E
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
AARE/ASDCAS/ASADS/
ASRE
§
AAOE/ASDRAS/ASOE
§
AAWE/ASDWE/ASWE
§
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
BE1
BE2
BE3
BE4
Q1
Q2
Q3
Q4
9
1
4
5
8
9
6
7
3
1
2
EA1
EA2
EA4
8
READ latency = 2
EA3
Figure 7
9. Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2)
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