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參數資料
型號: TMP435ADGST
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO10
封裝: GREEN, PLASTIC, MSOP-10
文件頁數: 13/31頁
文件大小: 477K
代理商: TMP435ADGST
SBOS495A – MARCH 2010 – REVISED APRIL 2010
www.ti.com
Bus Overview
Two-Wire Interface Slave Device Addresses
The TMP435 is SMBus interface-compatible. In
The TMP435 supports nine slave device addresses
SMBus protocol, the device that initiates the transfer
and is available in two different fixed serial interface
is called a master, and the devices controlled by the
addresses.
master are slaves. The bus must be controlled by a
The A1 and A0 pins, as summarized in Table 14), set
master device that generates the serial clock (SCL),
the slave device address for the TMP435.
controls the bus access, and generates the START
and STOP conditions.
Table 14. Two-Wire Addresses
To address a specific device, a START condition is
A0
A1
ADDRESS
initiated. START is indicated by pulling the data line
0
1001 100
(SDA) from a high to low logic level while SCL is
0
1
1001 101
high. All slaves on the bus shift in the slave address
byte, with the last bit indicating whether a read or
1
0
1001 110
write operation is intended. During the ninth clock
1
1001 111
pulse, the slave being addressed responds to the
0
Z
1001 000
master by generating an Acknowledge and pulling
Z
0
1001 001
SDA low.
1
Z
1001 010
Data transfer is then initiated and sent over eight
Z
1
1001 011
clock pulses followed by an Acknowledge bit. During
Z
0110 111
data transfer SDA must remain stable while SCL is
high, because any change in SDA while SCL is high
is interpreted as a control signal.
Read/Write Operations
Once all data have been transferred, the master
Accessing a particular register on the TMP435 is
generates a STOP condition. STOP is indicated by
accomplished by writing the appropriate value to the
pulling SDA from low to high, while SCL is high.
Pointer Register. The value for the Pointer Register is
the first byte transferred after the slave address byte
Serial Interface
with the R/W bit low. Every write operation to the
TMP435 requires a value for the Pointer Register
The TMP435 operates only as a slave device on
(see Figure 16).
either the two-wire bus or the SMBus. Connections to
either bus are made via the open-drain I/O lines, SDA
When reading from the TMP435, the last value stored
and SCL. The SDA and SCL pins feature integrated
in the Pointer Register by a write operation is used to
spike suppression filters and Schmitt triggers to
determine which register is read by a read operation.
minimize the effects of input spikes and bus noise.
To change the register pointer for a read operation, a
The TMP435 supports the transmission protocol for
new value must be written to the Pointer Register.
fast (1kHz to 400kHz) and high-speed (1kHz to
This transaction is accomplished by issuing a slave
3.4MHz) modes. All data bytes are transmitted MSB
address byte with the R/W bit low, followed by the
first.
Pointer
Register
byte.
No
additional
data
are
required. The master can then generate a START
condition and send the slave address byte with the
Serial Bus Address
R/W bit high to initiate the read command. See
To communicate with the TMP435, the master must
Figure 17 for details of this sequence. If repeated
first address slave devices via a slave address byte.
reads from the same register are desired, it is not
The slave address byte consists of seven address
necessary to continually send the Pointer Register
bits, and a direction bit indicating the intent of
bytes, because the TMP435 retains the Pointer
executing a read or write operation.
Register value until it is changed by the next write
operation. Note that register bytes are sent MSB first,
The address of the TMP435 is 4Ch (1001100b).
followed by the LSB.
20
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TMP435
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