- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382647 > TMPP320C6202BGLW167 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSORS PDF資料下載
參數(shù)資料
| 型號(hào)： | TMPP320C6202BGLW167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 58/83頁(yè) |
| 文件大小： | 1176K |
| 代理商： | TMPP320C6202BGLW167 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)當(dāng)前第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles
(see Figure 29)
NO.
150
167
UNIT
MIN
MAX
3
t
oh(HOLDAL-HOLDL)
Output hold time, HOLD low after HOLDA low
E
ns
E = ECLKIN period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 29)
NO.
PARAMETER
150
167
UNIT
MIN
2E
MAX
1
2
4
5
t
d(HOLDL-EMHZ)
t
d(EMHZ-HOLDAL)
t
d(HOLDH-EMLZ)
t
d(EMLZ-HOLDAH)
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
§
ns
ns
ns
ns
0
2E
7E
2E
2E
0
E = ECLKIN period in ns
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6211/C6211B
C6211/C6211B
1
3
2
5
4
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 29. HOLD/HOLDA Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMX320C6202BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6203BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6202BGLZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6203BGNZ167 | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMPR28051 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| TMPR28051-3-SL5 | 制造商:AGERE 制造商全稱:AGERE 功能描述:TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device |
| TMPR28051-SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET MAPPER|QFP|208PIN|PLASTIC |
| TMPR3904F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC |
| TMPR3907F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|QFP|208PIN|PLASTIC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。