
INTEGRATED CIRCUIT
TECHNICAL DATA
EJC-TMPR3904AF-1
14-Dec-1998
TOSHIBA CORPORATION
The information contained herein is presented only as a guide for the application of our
products. No responsibility is assumed by TOSHIBA for any infringements of patents or
other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
TMPR3904AF
(32 bit TX System RISC)
1. GENERAL DESCRIPTION
The TMPR3904AF (to be called TX3904A hereinafter) is a standard micro controller of the 32-
bit RISC Microprocessor TX39 family. The TX3904A uses the TX39 Processor Core as the CPU.
The TX39 Processor Core is a RISC CPU core Toshiba developed based on the R3000A
architecture of MIPS Technologies, Inc. As micro-controllers that can be embedded, besides the
TX39 Processor Core, the TX3904A has built-in peripheral circuits such as memory controllers,
DMA controllers, serial ports, and timers/counters.
2. FEATURES
n
Built-in TX39 Processor Core
Toshiba has uniquely developed this on the basis of the R3000A architecture of the MIPS.
Instruction cache 4KB/Data cache 1KB
Built-in debug support unit
n
DRAM Controller
Four-bank x two-channel configuration
Fast page mode/Hyper page (EDO) mode support
n
ROM Controller
Two-bank x two-channel configuration
Mask ROM, EPROM, E
2
PROM, Flash Memory, SRAM support
Page mode ROM support
n
DMA Controller
Independent four channels
Single address mode/Dual address mode
n
Interrupt Controller
Internal nine sources, external eight sources
Non-maskable interrupt (NMI)
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the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
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The information contained herein is subject to change without notice.