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參數(shù)資料
| 型號： | TMS29F800T-100CDBJQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| 中文描述： | 1048576 8位/ 524288由16位閃存 |
| 文件頁數(shù)： | 1/51頁 |
| 文件大小： | 685K |
| 代理商： | TMS29F800T-100CDBJQ |
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Single Power Supply Supports 5 V
Read/Write Operation
Organization . . .
Array-Blocking Architecture
– One 16K-Byte/One 8K-Word Boot Sector
– Two 8K-Byte/4K-Word Parameter Sectors
– One 32K-Byte/16K-Word Sector
– Fifteen 64K-Byte/32K-Word Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
Sector Protection
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
Fully Automated On-Chip Erase and
Program Operations
100 000 Program/Erase Cycles
Low Power Dissipation
– 40-mA Typical Active Read for Byte Mode
– 50-mA Typical Active Read for Word
Mode
– 60-mA Typical Program/Erase Current
– Less Than 100-
μ
A Standby Current
– 5
μ
A in Deep Power-Down Mode
All Inputs/Outputs TTL-Compatible
10%
1048576 By 8 Bits
524288 By 16 Bits
Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
Package Options
– 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
– 48-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
– Hardware Method for Detection of
Program/Erase Cycle Completion
Through Ready/Busy (RY/BY) Output Pin
High-Speed Data Access at 5-V V
CC
at Three Temperature Ranges
– 80 ns
Commercial . . . 0
°
C to 70
°
C
– 90 ns
Commercial . . . 0
°
C to 70
°
C
– 100 ns
Extended . . . –40
°
C to 85
°
C
– 120 ns
Automotive . . . –40
°
C to 125
°
C
10%
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
P
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright
1997, Texas Instruments Incorporated
A[0:18]
BYTE
DQ[0:14]
DQ15/A–1
Address Inputs
Byte/Word Enable
Data In/Data out
Data In/Out (Word-Wide Mode)
Low-Order Address (Byte-Wide Mode)
Chip Enable
Output Enable
No Internal Connection
Reset/Deep Power Down
Ready/Busy Output
Power Supply
Ground
Write Enable
CE
OE
NC
RESET
RY/BY
VCC
VSS
WE
PIN NOMENCLATURE
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