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1
TMS320C6421 Fixed-Point Digital Signal Processor
1.1 Features
High-Performance Digital Signal Processor
(C6421)
–
2.5-, 2.-, 1.67-ns Instruction Cycle Time
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400-, 500-, 600-MHz C64x+ Clock Rate
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Eight 32-Bit C64x+ Instructions/Cycle
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3200, 4000, 4800 MIPS
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Fully Software-Compatible With C64x
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Commercial and Automotive (Q or S suffix)
Grades
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+ DSP Core
–
Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
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Load-Store Architecture With Non-Aligned
Support
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64 32-Bit General-Purpose Registers
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Instruction Packing Reduces Code Size
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All Instructions Conditional
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Additional C64x+ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Auto-Focus Module Operation
C64x+ Instruction Set Features
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Byte-Addressable (8-/16-/32-/64-Bit Data)
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8-Bit Overflow Protection
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Bit-Field Extract, Set, Clear
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Normalization, Saturation, Bit-Counting
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VelociTI.2 Increased Orthogonality
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C64x+ Extensions
Compact 16-bit Instructions
Additional Instructions to Support
Complex Multiplies
TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346C–JANUARY 2007–REVISED NOVEMBER 2007
C64x+ L1/L2 Memory Architecture
–
128K-Bit (16K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
–
384K-Bit (48K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
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512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Endianess: Supports Both Little Endian and
Big Endian
External Memory Interfaces (EMIFs)
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16-Bit DDR2 SDRAM Memory Controller
With 128M-Byte Address Space (1.8-V I/O)
Supports up to 266-MHz (data rate) bus
and interfaces to DDR2-400 SDRAM
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Asynchronous 8-Bit-Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
Flash Memory Interfaces
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NOR (8-Bit-Wide Data)
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NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit
(I
2
C Bus )
Multichannel Buffered Serial Port (McBSP0)
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I2S and TDM
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AC97 Audio Codec Interface
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SPI
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Standard Voice Codec Interface (AIC12)
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Telecom Interfaces – ST-Bus, H-100
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128 Channel Mode
Multichannel Audio Serial Port (McASP0)
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Four Serializers and SPDIF (DIT) Mode
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet MAC (EMAC)
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IEEE 802.3 Compliant
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Supports Multiple Media Independent
Interfaces (MII, RMII)
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Management Data I/O (MDIO) Module
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