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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 1/35頁 |
| 文件大小： | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 8M
×
16-Bit
Maximum Addressable External Program
Space
16K x 16-Bit On-Chip ROM
32K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Three Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface With 16-Bit Data/Addressing
– One 16-Bit Timer
– Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
(JTAG) Boundary Scan
Logic
33-ns Single-Cycle Fixed-Point Instruction
Execution Time (30 MIPS)
1.2-V Core Power Supply
1.2-V to 2.75-V I/O Power Supply Enables
Operation With a Single 1.2-V Supply or
With Dual Supplies
Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
description
The TMS320UVC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UVC5409 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low power
consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage
enables it to operate with a single 1.2-V power supply or with dual power supplies for mixed voltage systems.
This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V
systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
A
Copyright
1999, Texas Instruments Incorporated
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
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