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參數資料
| 型號： | TMS3637DR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 搖控器 |
| 英文描述： | INFRARED, TRANSMITTER/RECEIVER IC, PDSO8 |
| 封裝： | PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 10/54頁 |
| 文件大小： | 384K |
| 代理商： | TMS3637DR |
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5–1
5 Principles of Operation
5.1
Power-On Reset
The power-on reset function starts when VCC rises above 2.7 V and is completed after four clock periods.
After power-on reset, the nine configuration bits contained in the EEPROM memory are loaded into the logic
circuits, which determine the device mode and configuration of operation. For correct enabling of the
power-on reset operation, it is necessary for VCC to first fall below 2.3 V and remain in this condition for at
least 0.5 ms.
5.2
EEPROM Memory (31 Bits)
The EEPROM memory contains a total of 31 bits. The first 22 of the 31 bits contain the security code. These
22 bits are named C01, C02,...C22, and are user definable. The last 9 bits of the total 31 bits are
configuration bits named CA,CB,...CI, and are also user definable to select the mode of operation for the
device.
5.2.1
Program Read Mode
The procedure described in the following steps is used to read the current contents of the EEPROM memory.
This can verify that the correct 22 security codes and 9 configuration bits are stored in memory (see
Figure 5–1):
1.
Set VCC to 5 V.
2.
Apply VCC + 0.5 V to OSCC. Wait at least 50 ms to allow the device to assume the read mode
(tsu2 > 50 ms). This voltage on OSCC forces the device into the read mode, and the terminals
are in the following configuration:
OSCR: program/read external clock input
OUT: serial output of 31 data bits currently stored in EEPROM
3.
Apply four reset pulses to OSCR (tw4 = tw5 = 10 s). This only needs to be done once during each
read operation.
4.
Apply 31 clock pulses to clock input OSCR (tw4 = tw5 = 10 s min). This clocks out the 31 data
bits (C01,C02,...C22, and CA,CB,...CI) that are stored in memory. Output data changes state
only on falling edge of clock pulses, except on data bit C01. If used, data bit C01 goes high on
the rising edge of the clock pulse.
NOTE:
Each succeeding group of 31 clock pulses, when applied, clocks out the data again
without any reset pulses required.
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