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參數資料
| 型號： | TMS664814DGE-8 |
| 英文描述： | SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
| 中文描述： | 內存| 4X2MX8 |的CMOS |的TSOP | 54PIN |塑料 |
| 文件頁數： | 1/56頁 |
| 文件大?。?/td> | 958K |
| 代理商： | TMS664814DGE-8 |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Organization . . .
1048576 x 16 Bits x 4 Banks
2097152 x 8 Bits x 4 Banks
4194304 x 4 Bits x 4 Banks
3.3-V Power Supply (
±
10% Tolerance)
Four Banks for On-Chip Interleaving for
x8/x16 (Gapless Access) Depending on
Organizations
High Bandwidth – Up to 125-MHz Data
Rates
Burst Length Programmable to 1, 2, 4, 8
Programmable Output Sequence – Serial or
Interleave
Chip-Select and Clock-Enable for
Enhanced-System Interfacing
Cycle-by-Cycle DQ Bus Mask Capability
Only x16 SDRAM Configuration Supports
Upper-/Lower-Byte Masking Control
Programmable CAS Latency From Column
Address
Performance Ranges:
Pipeline Architecture (Single-Cycle
Architecture)
Single Write/Read Burst
Self-Refresh Capability (Every 16 s)
Low-Noise, Low-Voltage
Transistor-Transistor Logic (LVTTL)
Interface
Power-Down Mode
Compatible With JEDEC Standards
16K RAS-Only Refresh (Total for All Banks)
4K Auto Refresh (Total for All Banks)/64 ms
Automatic Precharge and Controlled
Precharge
Burst Interruptions Supported:
– Read Interruption
– Write Interruption
– Precharge Interruption
Support Clock-Suspend Operation (Hold
Command)
Intel PC100 Compliant (-8 and -8A parts)
SYNCHRONOUS
CLOCK CYLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
tCK3
8 ns
tCK2
10 ns
tAC3
6 ns
tAC2
6 ns
tREF
64 ms
’664xx4-8
’664xx4-8A
8 ns
15 ns
6 ns
7.5 ns
64 ms
’664xx4-10
10 ns
15 ns
7.5 ns
7.5 ns
64 ms
description
The TMS664xx4 series are 67108864-bit synchronous dynamic random-access memory (SDRAM) devices
which are organized as follow:
Four banks of 1 048 576 words with 16 bits per word
Four banks of 2097152 words with 8 bits per word
Four banks of 4194304 words with 4 bits per word
All inputs and outputs of the TMS664xx4 series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high-performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and to enhance use with high-speed
microprocessors and caches.
The TMS664xx4 SDRAM is available in a 400-mil, 54-pin surface-mount thin small-outline package (TSOP)
(DGE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相關代理商/技術參數 |
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| TMS664814DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X2MX8|CMOS|TSOP|54PIN|PLASTIC |
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| TMS6708-25DJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| TMS6708-25N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| TMS6787-15N | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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