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參數(shù)資料
型號： TMX320C6201GNY167
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 24/83頁
文件大?。?/td> 1176K
代理商： TMX320C6201GNY167
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
TIMER 1
TOUT1
TINP1
F1
F2
O
I
IPD
IPD
Timer 1 or general-purpose output
Timer 1 or general-purpose input
TIMER 0
TOUT0
TINP0
G1
G2
O
I
IPD
IPD
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
IPD
External clock source (as opposed to internal)
IPD
Receive clock
IPD
Transmit clock
IPU
Receive data
IPU
Transmit data
IPD
Receive frame sync
IPD
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
IPD
External clock source (as opposed to internal)
IPD
Receive clock
IPD
Transmit clock
IPU
Receive data
IPU
Transmit data
IPD
Receive frame sync
IPD
Transmit frame sync
RESERVED FOR TEST
IPU
Reserved (leave unconnected,
do not
connect to power or ground)
IPU
Reserved (leave unconnected,
do not
connect to power or ground)
IPU
Reserved (leave unconnected,
do not
connect to power or ground)
Reserved (leave unconnected,
do not
connect to power or ground)
Reserved (leave unconnected,
do not
connect to power or ground)
Reserved (leave unconnected,
do not
connect to power or ground)
Timer 0 or general-purpose output
Timer 0 or general-purpose input
CLKS1
CLKR1
CLKX1
DR1
DX1
FSR1
FSX1
E1
M1
L3
M2
L2
M3
L1
I
I/O/Z
I/O/Z
I
O/Z
I/O/Z
I/O/Z
CLKS0
CLKR0
CLKX0
DR0
DX0
FSR0
FSX0
K3
H3
G3
J1
H2
J3
H1
I
I/O/Z
I/O/Z
I
O/Z
I/O/Z
I/O/Z
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
C12
D12
A5
D3
N2
Y20
O
O
O
O
O
O
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