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參數資料
| 型號： | TMX320C6202BGDP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 34/83頁 |
| 文件大小： | 1176K |
| 代理商： | TMX320C6202BGDP167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
power-down mode logic
Figure 7 shows the power-down mode logic on the C6211/C6211B.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN
RESET
PD3
Internal
Peripherals
Clock
Distribution
and Dividers
TMS320C6211/C6211B
CLKOUT2
CLKOUT1
External input clocks, with the exception of CLKIN, are
not
gated by the power-down mode logic.
Figure 7. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15
10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 20.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU
and Instruction Set Reference Guide
(literature number SPRU189).
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